COOL Chips XI
April 16 - 18, 2008
Yokohama Joho Bunka Center, Yokohama, JAPAN
April 16, 2008
Special Session 1
Chair: Koji Inoue (Kyushu University)
Challenges and Approaches in Providing Scalability and Quality of Service in Chip Multi-Processor Systems
Speaker: Yan Solihin (North Carolina State University, U.S.A.)
Special Session 2
Chair: Koji Inoue (Kyushu University)
Massively Parallel Graphics Processors in a Multicore, Power-limited Era
Speaker: Kevin Skadron (University of Virginia / NVIDIA, U.S.A.)
April 17, 2008
Session I
Welcome and Opening Remarks
Chair: Kazumasa Suzuki (NEC)
Tadao Nakamura, Chair of the Organizing Committee
Lily Jow,Chair of TCMCOMP, The IEEE Computer Society
Makoto Ando,President of Electronics Society, IEICE
Hiroshi Nakada, Mayor of Yokohama City
Keynote Presentation 1
Chair: Yusuke Nitta (Renesas Technology)
Co-design of "Hard Software" and "Soft Hardware" to Realize the
Convergence and Divergence of Modern Applications
Satoru Ito (Renesas Technology)
Keynote Presentation 2
Yoshio Hirose (Fujitsu Laboratories)
Anatomy of a Brain-like Computer
Hiroshi Tsujino (Honda)
Session II : Poster Short Speeches
Chair: Toshinori Sato (Fukuoka University)
Poster 1 Prototyping Asynchronous Circuits on COTS FPGAs
Young Woo Kim, Seongwoon Kim (Electronics and Telecommunications Research Institute, Korea)
Poster 2 Unified Architecture for Video Coding
Jian Huang, Jooheung Lee (University of Central Florida, U.S.A.)
Poster 3 A High Throughput FPGA Architecture for DBP Application
Yidong Liu, Jooheung Lee (University of Central Florida, U.S.A.)
Poster 4 Design of an Ultra High Speed Crypto-Processor ASIC
Liakot Ali, Niranjon Roy (Bangladesh University of Engineering and Technology,Bangladesh)
Poster 5 Power Efficient Integrated Motion Compensator for MPEG and H.264/AVC
Kwang Woo Lee, Myung H. Sunwoo (Ajou University, Korea)
Poster 6 A Dual-Field Multiplier for GF(P) and GF(2m)
Che Wun Chiou, Chiou-Yng Lee, Jim-Min Lin (Ching Yun University, Lunghwa University of Science and Technology, and Feng Chia University, Taiwan)
Poster 7 Using Independent Bodies in Bulk-CMOS Gates
D. Guerrero, A. Millan, J. Juan, M. J. Bellido, J. Viejo, A. Muñoz (Universidad de Sevilla, Spain)
Poster 8 Leakage-aware Multi-level Logic Minimization based on BDD Manipulation
Saurabh Chaudhury, Santanu Chattopadhyay (IIT, India)
Poster 9 Dynamic Power Analysis of Embedded Systems Based on Instruction Execution Driven Simulation
Yasuhito OHMIYA, Hideharu AMANO (Mitsubishi Electric and o University)
Poster 10 Design of Booth’s Algorithm Using Lector Technique
B.Rajendra Naik, P.Chandrasekhar, Rameshwar Rao (Osmania University, India)
Poster 11 Design of an Automatic Instruction Selection Algorithm for Enhancing Arithmetic Performance
Yung Ching Yang, Chichyang Chen (Feng Chia University, Taiwan)
Poster 12 MOS Current Mode Logic based Elliptic Curve Cryptosystem Implementation
Stéphane Badel, Deniz Karakoyunlu, Frank K. Gürkaynak, Yusuf Leblebici (EPFL, Switzerland)
Poster 13 Internal Power Dissipation of Static CMOS Gates in UDSM Technologies
Alejandro Millan, Manuel J. Bellido, Jorge Juan, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo (Universidad de Sevilla, Spain)
Poster 14 Implementation of Echo Instructions into MIPS Processor
Arda Karaduman, Iver Stubdal, Hideharu Amano (Keio University)
Poster 15 Low Intrusive Real-Time Execution Tracer for UML-Based Embedded Software
Gang Zhang, Kohji Takano, Nobuyuki Ohba (IBM Japan)
Poster 16 A Wide Input Range CMOS OTA with PMOS Path Mobility Compensation
Doo-Hwan Kim, Sun-Geon Yoo, Kyoung-Rok Cho (Chungbuk National University,Korea)
Poster 17 Low-Power ECG Detector and its ADC for Low-Power Implantable Cardiac Pacemakers
Y. J. Min, H. K. Kim, C. R. Kim, Y. R. Kang, J. P. Son, S. W. Kim (Korea University, Korea)
Poster 18 Design of a (B)FSM-based Processing Engine
Konstantin Septinus, Ulrich Mayer, Cordt W. Starke, Peter Pirsch (University of Hannovers and IBM Deutschland Entwicklung, Germany)
Poster 19 A QoS Control Method for a Heterogeneous SMT Processor
Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (Nara Institute of Science and Technology)
Poster 20 A Run-time Power Gating Sleep Control Scheme on Cache Controller
Lei Zhao, Xu Hui, Nanomi Seki, Yoshiki Saito (Keio University and Shibaura Institute of Technology)
Poster 21 A Hybrid Platform for Practical Evaluation of Processors
Akihito Ichiki, Takashi Nakada, Yasuhiko Nakashima (Nara Institute of Science and Technology)
Poster 22 Low Power Technique of TLB for Embedded Processor
Xu Hui, Lei Zhao, Seki Naomi, Hideharu Amano, Mitaro Namiki, Kimiyoshi Usami (Keio University, Tokyo University of Agriculture & Technology and Shibaura Institute of Technology)
Poster 23 CMP L2 NUCA Cache Power Consumption Reduction Technique
P. Foglia, C.A. Prete, M. Solinas, F. Panicucci (University of Pisa, IMT Lucca, Italy)
Session III: Low Power Cache and Circuits
Co-Chairs: Kyoung-Rok Cho (Chungbuk National Universit), Koji Hirairi (Sony), Hiroshi Kawaguchi (Kobe University)
A Novel Linked-Entry Frequently Executed Instruction Table Design for Conflict Avoidance and Low Energy Consumption
Ching-Wen CHEN, Chang-Jung KU, Ming-Chi HUANG (Feng Chia University, Taiwan)
A Leakage-Aware Shared L2 Cache Management Scheme for Low-Power Chip Multiprocessors
Hee-Joon Kang, Wonil Choi, Jihong Kim (Seoul National University, Korea)
A Fast Conversion Time Pipeline TDC based All-Digital CMOS Temperature Sensor
Kyoung-Jin Lee and Soo-Won Kim (Korea University, Korea)
High Speed Glitchless Clock Multiplexer Optimized for Synchronous and Asynchronous Clocks
Takeo Yasuda (IBM Japan)
Session IV: Special Featured Processors
Chais: Keiji Kimura (Waseda University)
Ethernet Bridge Chip for I/O Virtualization with Throughput Enhancement
Jun Suzuki, Hideyuki Shimonishi, Yoichi Hidaka, Junichi Higuchi, Takashi
Yoshikawa, Atsushi Iwata (NEC)
A Single Chip Fail-Safe Microprocessor with Duplicated Peripheral Modules and IO Buses
Kotaro Shimamura (Hitachi)
Session V
Chair: Kazumasa Suzuki (NEC)
Invited Presentation 1
Architecture of a Highly Parallel Array Processor IMAPCAR and its Technology Perspective
Shorin Kyo (NEC)
Session VI: Media Processors
Chair: Makoto Ikeda (University of Tokyo)
A Fully-Programmable Digital Image Processor with full HD 1080p Processing Capabilities
Sumito Arakawa, Yuji Yamaguchi, Satoshi Akui, Yasushi Fukuda, Hirofumi Sumi, Hiroshi Hayashi, Masahiro Igarashi, Kei Ito, Hidetoshi Nagano, Masatoshi Imai, Naosuke Asari (Sony)
Multi-stream/multi-format Video Entropy Engine for Mobile application
Kyung-koo Lee (Samsung, Korea)
Reducing the Power Consumption of Mixed Signal Audio Codecs
Gordon R. McLeod (Wolfson Microelectronics, U.K.)
Professional H.264/AVC Decoder LSI for High-quality HDTV Broadcast Infrastructure
Hiroe Iwasaki, Mitsuo Ikeda, Koyo Nitta, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Takeshi Yoshitome, Hiroaki Matsuda and Jiro Naganuma (NTT)
April 18, 2008
Session VII
Chair: Yasuo Unekawa (Toshiba)
Keynote Presentation 3
Multicore Compiler for Low Power High Performance Embedded Computing
Hironori Kasahara (Waseda University)
Session VIII
Chair: Jiro Naganuma (NTT)
Invited Presentation 2
Intel Centrino Atom processor technology -- Enabling the Best Internet Experience in Your Pocket
Ticky Thakkar (Intel, U.S.A.)
Session IX: Multicore Software
Chair: Takeshi Kodaka (Toshiba)
An 8 CPU SoC with Independent Power-off Control of CPUs and Multicore Software Debug Function
Yutaka Yoshida, Masayuki Ito, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori, Jun Sakiyama, Masashi Takada, Kunio Uchiyama, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Renesas Technology, Hitachi and Waseda University)
Thread Interpreter A New Multithread Programming Model and Runtime Environment for Multi-core
Ryuji Sakai, Nobuhiro Kato, Tomofumi Shimada (Toshiba)
Session X
Chair: Masato Suzuki (Matsushita Electric Industrial)
Invited Presentation 3
The Strategy, Reasoning and Principles of the ARM MP Core Technology
John Goodacre (ARM, U.K.)
Session XI: Multicore Processors
Co-Chairs: Hiroaki Suzuki (Renesas Technology), Hajime Shimada (Kyoto University)
A Low-power Mobile Multimedia Processor for Scalable Multi-core System
Soichiro Hosoda, Kenta Yasufuku, Masato Uchiyama, Jun Tanabe, Takanori
Tamai, Takaaki Matsumoto, Takashi Miyamori, Masaki Nakagawa (Toshiba)
High Performance and Low Power SH2A-DUAL Core for Embedded Microcontrollers
Kesami Hagiwara, Yoshikazu Kiyoshige, Takeshi Kataoka, Toru Hiraoka, HisakazuSato, Hiromichi Yamada, Yasuo Sugure, Shunichi Iwata Toshihiro Hattori (Renesas Technology)
Low power and high performance techniques on a mobile handset LSI, Medity M2
Taku Ohsawa, Shuichi Kunie, Tatsuya Tokue (NEC)
XScale: Ultra Low Power Design Techniques
Jack Kang, Junjing Yan, Hongyi Chen (Marvell Semiconductor, U.S.A.)
Session XII: Panel Discussions
Organizer: Josep Torrellas (University of Illinois, U.S.A.)
Panelists:
Hironori Kasahara (Waseda University)
Toshihiro Hattori (Renesas Technology)
Hisashige Ando (Fujitsu)
Yukoh Matsumoto (TOPS Systems)
John Goodacre (ARM, U.K.)
Ticky Thakkar (Intel, U.S.A.)
Yan Solihin (North Carolina State University, U.S.A.)
Closing Remark
Kunio Uchiyama, Program Committee Co-Chair (Hitachi)