COOL Chips IV
April 19 - 20, 2001
Kikai-Shinko-Kaikan, Tokyo, JAPAN
Session I : Plenary Session
Co-Chairs: Gensuke Goto (Fujitsu) and Shuhei Iwade (Mitsubishi Electric)
Welcome and Opening Remarks
Tadao Nakamura, Chair of the Organizing Committee
Koichi Nagasawa,Chair of Electron Devices Executive Committee, JEITA
Satoshi Iwata, Director, METI, Japan
Hiroshi Ishihara,President of Electronics Society, IEICE
Allen J.Baum, Chair of TCMM, IEEE Computer Society
Keynote Presentation 1
Silicon on Insulator Technology for the Pervasive Systems' Technology
Ghavam Shahidi (Director, IBM Microelectronics)
Session II : Benchmarks for Embedded Processors
Chair: Hirohisa Gambe (Fujitsu)
Invited Presentation 1
Analyzing Processors and Compilers/Toolchains Using EEMBC Benchmarks:Performance, Code Size, and Power Consumption Tradeoffs
Alan Weiss (Chairman and CTO, EEMBC Certification Labs)
Session III : Poster Short Speech
Chair: Masatoshi Sekine (Tokyo Univ. of Agr. & Tech.)
Poster 1:Hardware Resource and Performance Optimization for Elliptic Curve Cryptography
Kohji Takano, Akashi Satoh, and Nobuyuki Oba (IBM Japan)
Poster 2: A Data Prefetch Supported with Fast DMA Technique For High-Speed Network Interface Design
Ali Elkateeb and Mohammed Elbeshti (Univ. of Michigan－Dearborn)
Poster 3:Overview of SpecC* Technology Open Consortium
Tadatoshi Ishii (Toshiba)
Poster 4: A High Speed Programmable Timing Generator
Sun Jing and Chin Hsi Ling, Edward (Nanyang Tech. Univ.)
Poster 5: Case Study: Mapping Telecommunication Functions to Fine Grain Multiprocessor System (FPSA)
Hiroki Akaboshi, Yuji Kawazu, Kei Yamanaka, Tadaaki Tsuchiya (Logic Research), Hiroshi Date, Koji Inoue and Takanori Hayashida (ISIT)
Poster 6: The KIT COSMOS Processor: Eliminating Ineffectual Branch
Toshiyuki Yamamoto, Toshinori Sato, Itsujiro Arita (Kyushu Inst. of Tech.)
Poster 7:VLSI and High Speed Arithmetic
Albert A. Liddicoat and Michael J. Flynn (Stanford Univ.)
Session IV : Digital Signal Processors
Chair: Hajime Kubosawa (Fujitsu)
Architecture and Design of DSP Core for 3G Wireless Application
Shigeshi Abiko (Texas Instruments Japan)
Low Power and High Speed Fully Synthesizable DSP Cores
David Dahan (DSP Group)
C166S_V2: A single cycle 16-Bit Microcontroller and DSP core for next generation Systems on Chips
Klaus Maier (Infineon Technologies)
Session V : Emerging Processor Architectures
Chair: Hideharu Amano (Keio Univ.)
A High Performance 3D Graphics Rasterizer with Effective Memory Structure
Sung-Bong Yang, Woo-Chan Park, Kil-Whan Lee, Seung-Gi Lee, Moon-Hee Choi, Won-Jong Lee, Cheol-Ho Jeong, Byung-Uck Kim, Woo-Nam Jung, Il-San Kim, Won-Ho Chun, Won-Suk Kim, Tack-Don Han, Moon-Key Lee, and Shin-Dug Kim (Yonsei Univ.)
SIMD ISA Extensions: Reducing Power Consumption on a Superscalar Processor for Multimedia applications
Julien Sebot, Nathalie Drach (LRI Univ. Paris XI)
Single-port and Multi-port Memories Synthesis for Low Power
Wen-Tsong Shiue (Silicon Metrics)
Give up Meeting Timing Constraints, but Tolerate Violations
Toshinori Sato, Itsujiro Arita (Kyushu Inst. of Tech.)
Session VI : Panel Discussion
Chair and Organizer: Shuichi Sakai (Univ. of Tokyo)
“ What is the Ability of a Processor Chip?
Panelist:
Kei Hiraki (Univ. of Tokyo)
Alan Weiss (EEMBC Certification Labs)
Andrew Shaw (Transmeta)
Hideharu Amano (Keio Univ.)
Satoshi Matsuoka (Tokyo Inst. of Tech.)
Satoshi Matsushita (NEC)
Fumio Arakawa (Hitachi)
April 20, 2001
Session VII : Special Keynotes
Co-Chairs: Katsuro Sasaki (Hitachi) and Takeshi Ogura (NTT)
Keynote Presentation 2
SOC strategy in Korea (from Samsung Electronics’ perspective)
Hyung-Lae Roh (Sr. Vice President, Samsung Electronics)
Keynote Presentation 3
Research and development of entertainment robots and their requirements to LSI
Tadashi Otsuki (Dep. President, Entertainment Robot Company, Sony)
Session VIII : New Wave in PC-Chips
Chair: Masasuke Kishi (Oki Electric)
Invited Presentation 2
Richard Brown (Director of Marketing, VIA Technologies)
Session IX : Low Power Architectures
Chair: Kazumasa Suzuki (NEC)
ChipOS: Open Power-Management Platform for Future System-On-a-Chip Designs
Hiroyuki Mizuno (Hitachi)
VR4131: Ultra Low Power Consumption Style Processor
Kota Hamaya and Masakazu Chiba (NEC IC Microcomputer Systems)
Session X: Processor Architectures
Chair: Tomohiro Kudoh (RWCP)
Branch Micro-architecture of SH5 Embedded Processor
Naohiko Irie (Hitachi)
ASCA chip set: Key Components of Multiprocessor Architecture for Multi-grain Parallel Processing
Tsuyoshi Abe, Hideharu Amano (Keio Univ.)
Session XI: Wireless Communication Systems
Chair: Chin-yin Tsui (Hong Kong Univ. of Sci. & Tech.)
Single Chip Programmable Baseband ASSP for 5GHz Wireless LAN Applications
Johannes Kneip, Matthias Weiss, Wolfram Drescher, Volker Aue, Jurgen Strobel, Michael Bolle and Gerhard Fettweis (Systemonic AG)
A W-CDMA Baseband Modem LSI with Multi-Engine Architecture
May Suzuki, Manabu Kawabe, Takashi Yano, Junko Kiyota, Hirotake Ishii, Tsuyoshi Tamaki and Nobukazu Doi (Hitachi)
Session XII : Media Processors
Chair: Masaitsu Nakajima (Matsushita Electric)
The Performance and Power Consumption of the Trimedia TM32 VLIW Media Processor Core
Kees A. Vissers (TriMedia Technologies)
A 4GOPS 3Way-VLIW Image Recognition Processor based on a Configurable Media-processor
Hiroyuki Takano, Y.Kondo, T.Miyamori, Y.Taniguchi, T.Kitazawa, S.Inoue, I.Katayama, K.Yahagi, A.Ooue, T.Tamai, K.Kohno, Y.Asao, H.Fujimura, H.Uetani, S.Asano, Y.Miyamoto, A.Yamaga, K.Maeda, Y.Masubuchi, T.Furuyama (Toshiba)
A Mixed-signal 0.18um CMOS SOC for DVD Systems with 432MS/s PRML Read Channel and 16Mb Embedded DRAM
Kozo Irie, Shin-ichi Gotoh, Toshihiko Takahshi, Kazuya Ohshima, Nobuhiro Mimura, Kazutoshi Aida, Toshinori Maeda, Takashi Yamamoto, Koji Sushihara, Yoichi Okamoto, Yasuhiro Tai, Takeshi Nakajima, Makoto Usui, Takahiro Ochi, Katsuhiko Komichi, Akira Matsuzawa (Matsushita Electric)
Multi-bank Memory Architecture of Embedded 20Mbit DRAM for MPEG-4 Codec LSI
Masayoshi Tojima and Akihiko Inoue (Matsushita Electric)
Closing Remarks
Eiji Masuda, Program Committee Chair