COOL Chips VII
April 15 - 17, 2004
Yokohama Joho Bunka Center, Yokohama, JAPAN
April 15, 2004
Session I : Plenary Session
Co-Chairs: Noriyoshi Ito (Oki Electric) and Yoshiaki Hagiwara (Sony)
Welcome and Opening Remarks
Tadao Nakamura,
Katsuhiro Shimohigashi,
Masayuki Izutsu,
Allen J. Baum,
Keynote Presentation 1
Energy Optimization in Multi-Core
John Cornish (ARM)
Session II :
Chair: Hajime Kubosawa (Fujitsu Labs.)
Invited Presentation 1
Dynamically Reconfigurable Processor DAP/DNA-2 and Development DAP/DNA-FW
Tomoyoshi Sato (IP Flex)
Session III: Reconfigurable Computing
Chair: Kiat Seng Yeo (Nanyang Technological University)
Stream Application Evaluation on the DRP-1
Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Katsuaki Deguchi, Kenichiro Anjo, Toru Awashima, and Hideharu Amano (Keio University)
Can A Cool Chip Be Hot? Yes, Flex Power FPGA Can.
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, and Hanpei Koike (AIST / Meiji University)
A low power AES circuit design for FPGA implementation
Toshihiro Katashita, Atsushi Maeda, Kenji Sayano, and Yoshinori Yamaguchi (University of Tsukuba / AIST)
Session IV: Poster Short Speeches
Chair: Yukihiro Iguchi (Meiji University)
Poster 1: SFL Centric HDL Based Design System and EDA Linux LiveCD
Naohiko Shimizu (Tokai University)
Poster 2: Experimental Results on Processor Test by BAST Scheme
Koichi Watanabe, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, and Kazuhiko Iwasaki (Tokyo Metropolitan University)
Poster 3: Queue Machine with Queue Extension Mechanism
Sotaro Kawata (The University of Tokyo) and Masahiro Sowa (The University of Electro-Communications)
Poster 4: Design and Implementation of Switching Fabrics for Multistage Interconnection Network with Directory Cache
M. Sumiyoshi, T. Midorikawa, and H. Amano (Keio University)
Poster 5: Low-Power Design of a Local-Timing Generator for Locally Timed Asynchronous Circuits
Masakazu Shimizu and Koki Abe (The University of Electro-Communications)
Poster 6: Can A Cool Chip be Hot? Yes, Flex Power FPGA Can.
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, and Hanpei Koike (AIST)
Poster 7: Intelligent Energy Management using Dynamic Voltage Scaling in an ARM Processor core
Tim Whitfield and David Flynn (ARM)
Poster 8: CHRONOS: An Asynchronous CPU Core Using Speculative Completion and Common Delay Techniques
Ken-ichiro Ishikawa, Jun-ichi Maruyama, Yoshinori Adachi, and Hideharu Amano (Keio University)
Poster 9:Exact Time-based Computations for Real Time Embedded Processors
Christopher E. Ackles and Albert A. Liddicoat (California Polytechnic State University San Luis Obispo)
Poster 10: Development of i8086 Compatible Processor for VLSI Design Education and System on Chip
Masashiro Ohyama and Naohiko Shimizu (Tokai University)
Poster 11: FPGA Based Encryption/Decryption Network Co-processor
Ming Y. Wong and Albert A. Liddicoat (California Polytechnic State University)
Poster 12: Implementation and Evaluation of Stochastic Simulation of Chemical Reaction Model on FPGA
M. Yoshimi, Y. Osana, T. Fukushima, and H. Amano (Keio University)
Poster 13: MegaProto: A Prototype of Ultra Low-Power Mega-Scale System
Yoshihiko Hotta, Mitsuhisa Sato, Taisuke Boku (University of Tsukuba),Hiroshi Nakashima (Toyohashi University of Techology), Hiroshi Nakamura (The University of Tokyo), Satoshi Matsuoka (Tokyo Institute of Technology), Daisuke Takahashi, Chikafumi Takahashi, Shin’ichi Miura, Yoshihiro Nakajima (University of Tsukuba), Masaaki Kondo(JST and The University of Tokyo), and Motonobu Fujita (The University of Tokyo)
Session V: Multimedia Chips
Chair: Fumio Arakawa (Hitachi)
VASA/ISIL: Single-chip MPEG-2 HDTV CODEC LSIs for Advanced Professional and Consumer Embedded Systems
Jiro Naganuma, Hiroe Iwasaki, Mitsuo Ikeda, Koyo Nitta, Ken Nakamura, TakeshiYoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Toshihiro Minami, Takaaki Izuoka, Makoto Endo, and Yoshiyuki Yashima (NTT Cyber Space Labs.)
A Low-Power MPEG-4 Codec IP Macro for VGA-Video Applications
Taro Hagiya, Toshiyuki Yoshitake, Yasuhiro Watanabe, Kiyonori Morioka, and Hiroshi Nakayama (Fujitsu Labs.)
Session VI: Panel Discussion
Outlook for low-power and high-performance processor design:
- How can we survive in an era of billion-transistor chips?
Chair and Organizer: Hiroaki Kobayashi (Tohoku University)
Panelists:
Hideharu Amano (Keio University)
Yasuhiko Hagihara (NEC)
Albert A. Liddicoat (California Polytechnic State University)
Wonyong Sung (Seoul National University)
Tack-Don Han (Yonsei University)
Osamu Takahashi (IBM Austin)
April 16, 2004
Session VII
Chair: Yasuo Unekawa (Toshiba)
Keynote Presentation 2
Cool Chips Enable Ubiquitous Web Browsing
Daniel F. Zucker (ACCESS)
Session VIII
Chair: Jun Iwamura (JEITA)
Invited Presentation 2
BioServer :
--- Packing a New Level of Processing in Small Footprint
--- Density-Intensive Computing for Bioinformatics
Masahito Kubo (Fujitsu)
Session IX
Chair: Masato Suzuki (Matsushita Electric)
Invited Presentation 3
Transmeta's Low Power Efficeon Microprocessor
David R. Ditzel (Transmeta)
Session X: Efficient Systems
Chair: Kimiyoshi Usami (Shibaura Institute of Technology)
12-Channel GPS Baseband with Acquisition, Tracking and Processor Units in 0.18um CMOS with sub-32mW Typical Power Consumption
Ilkka Saastamoinen, Juha Roström, Janne Järvenpää, and Jari Nurmi (u-Nav Microelectronics / Finland Tampere University of Technology)
An SOI Technology Based Time Code Receiver for High Sensitivity and Extremely Low Power Consumption Radio Controlled Clock
Junichi Yanagihara, Tokio Miyashita, and Takashi Taya (Oki Electric)
An Area and Energy Efficient IP Core for Scalar Product Computation
Jiangmin Gu, Chip-Hong Chang, and Kiat-Seng Yeo (Nanyang Technological University)
An Adder for a Redundant Digit Arithmetic Unit
Hossam A. H. Fahmy (Cairo University) and Michael J. Flynn (Stanford University)
Session XI: Processor Architecture
Chair: Kevin W. Rudd (Intel)
Pipeline Structure of SH-X Core for Achieving High Performance and Low Power
Motokazu Ozawa, Takahiro Irita, Kiwamu Takada, Hajime Yamashita, Tomoyuki Kodama, Tohru Hiraoka, Tatsuya Kamei, Osamu Nishii, Fumio Arakawa, aohiko Irie, and Toshihiro Hattori (Hitachi / Renesas Tech. / SuperH Japan)
A Hardware Accelerator for JavaTM Platforms on a Microprocessor Core for Mobile Applications
Tetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Kenji Kitagawa, Ryohei Yoshida, Motokazu Ozawa, Toru Hiraoka, Saneaki Tamaki, Keisuke Toyama, Motoaki Satoyama, Osamu Nishii, Fumio Arakawa, Shinichi Yoshioka, Toshihiro Hattori, and Kunio Uchiyama (Hitachi / Renesas Tech. /SuperH Japan)
Dynamic Cache Way Allocation for Power Reduction
Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Naoya Hattori, Shuichi Sakai, and Hidehiko Tanaka (The University of Tokyo)
A Super Instruction-Flow Architecture
Kenji Kise, Takahiro Katagiri, Hiroki Honda, and Toshitsugu Yuba (The University of Electro-Communications / JST)
Session XII: Embedded Processors & Cluster Computing
Chair: Makoto Ikeda (The University of Tokyo)
Measurement and Characterization of Power Consumption of Microprocessors for Power-aware cluster
Yoshihiko Hotta, Mitsuhisa Sato, Taisuke Boku, Daisuke Takahashi, and Chikafumi Takahashi (University of Tsukuba)
The Origin and Evolution of Green Destiny
Wu-chun Feng and Chung-hsing Hsu (Los Alamos National Laboratory)
A Very-Low-Latency Superscalar Microcontroller for Automotive, Industrial, and PC-Peripheral Applications
Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanaga Yamazaki, and Takanori Shimura (Hitachi / Renesas Tech.)
A Resume-Standby Application Processor for 3G Cellular Phones with Low Power Clock Distribution and On-Chip Memory Activation Control
Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Toru Hiraoka, Motokazu Ozawa, Tetsuya Yamada, Kenji Ogura,Masahide Abe, Tadashi Hoshi, Saneaki Tamaki, Mikio Furuyama, Naohiko Irie, Fumio Arakawa, Junichi Nishimoto, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, and Toshihiro Hattori (Hitachi / Renesas Tech. / SuperH Japan)
Closing Remarks
Kunio Uchiyama, Program Committee Chair