COOL Chips IX
April 19 - 21, 2006
Yokohama Joho Bunka Center, Yokohama, JAPAN
April 19, 2006
Special Session 1
Chair: Koji Inoue (Kyushu University)
Understanding Interactions between Power and Reliability Optimizations
Speaker: Vijaykrishnan Narayanan (Pennsylvania State University)
Special Session 2
Chair: Koji Inoue (Kyushu University)
Challenges and Opportunities of Multi-Core Processors
Speaker: Antonio González (Intel Corp. and Universitat Politècnica de Catalunya)
April 20, 2006
Session I
Welcome and Opening Remarks
Chair: Kazumasa Suzuki (NEC)
Tadao Nakamura,
Lily Jow,
Masataka Nakazawa,
Shunsuke Miyamoto,
Keynote Presentation 1
Chair: Yasuo Unekawa (Toshiba)
Recent Trends in Vehicle Electronics
Toshimi Abo (Nissan Motor Co., Ltd.)
Session II
Chair: Hajime Kubosawa (Fujitsu Lab.)
Invited Presentation 1
SoC, MCU technology for Automotive
Atsushi Hasegawa (Renesas Tech.)
Session III: Processors
Chair: Tomofumi Okuda (Sony)
SH-X2: A 90-nm SuperH Processor Core for Cellular Phones and Car Information Systems
Makoto Ishikawa, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Tetsuya Yamada, Kenji Ogura, Masahide Abe, Fumio Arakawa, Naohiko Irie, Junichi Nishimoto, Osamu Nishii, and Toshihiro Hattori (Hitachi / Renesas Technology / Hitachi ULSI Systems)
Security Enhanced Embedded Processor using Local Memory Protection Mechanism
Takeshi Kawabata, Takanori Tamai, Mikio Hashimoto, and Takashi Miyamori (Toshiba)
Increasing Exploitable Parallelism in Java Byte Codes with Micro-threading and an Advanced Stack Cache Architecture
Damien J. Uern and Amos R. Omondi (Flinders University / Yonsei University)
Session IV: Poster Short Speeches
Chair: Kenji Kise (Tokyo Institute of Technology)
Poster 1: Dynamic Charge Recovery Logic
Vishwanathan Mohan (Universita Delgi Studi di Genova)
Poster 2: Programmable Graphics Hardware for Image Synthesis Using the Global Illumination Model
Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Kenichi Suzuki, Nobuyuki Ohba, and Tadao Nakamura (Tohoku University)
Poster 3: Reducing Energy of Parallel Programs using Slack Reclamation by DVFS in a Power-scalable High Performance Cluster
Hideaki Kimura, Mitsuhisa Sato, Yoshihiko Hotta, Taisuke Boku, and Daisuke Takahashi (University of Tsukuba)
Poster 4: A Reconfigurable Java Environment for Embedded Systems
Shinsuke Nino, Junichi Sakamoto, Takayuki Mori, Yuichiro Shibata, and Kiyoshi Oguri (Nagasaki University)
Poster 5: Evaporative Cooling in Microfluidic Channels
George Maltezos, Aditya Rajagopal, and Axel Scherer (California Institute of Technology)
Poster 6: An Evaluation and Investigation of Dual-Thread Numerical Integration Mechanism for FPGA-based Biochemical Simulator ReCSiP
Y. Nishikawa, Y. Osana, M. Yoshimi, Y. Iwaoka, T. Kojima, A. Funahashi, N. Hiroi, Y. Shibata, N. Iwanaga, H. Kitano, and H. Amano (Keio University)
Session V: Low-Power Architecture
Chair: Hiroaki Suzuki (Renesas Tech.)
A Hybrid Power Reduction Scheme Using Pipeline Stage Unification and Dynamic Voltage Scaling
Hajime Shimada, Hideki Ando, and Toshio Shimada (Kyoto University /Nagoya University)
Reduce Static Power Dissipation of On-chip L2 Caches
Zhang Chengyi and Zhang Minxuan (National University of Defense Technology)
Session VI: Image Processing
Chair: Tsung-Han Tsai (National Central University)
An Architecture Study of Scalable Optical-Flow Processor for Real-Time Video Segmentation
Ryo Yamamoto, Yuki Fukuyama, Tadayoshi Katagiri, Junichi Miyakoshi, Yuki Kuroda, Noriyuki Minegishi, Masayuki Miyama, Hiroshi Kawaguchi, Kousuke Imamura, Hideo Hashimoto, and Masahiko Yoshimoto (Kobe University / Kanazawa University)
A 232MHz Variable Block Size Integer Motion Estimation Processor with System-in-Silicon DRAM for H.264/AVC
Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga, Kouichi Kumagai, Yoshihiro Mabuchi, and Kenji Yoshida (Waseda University /System Fabrication Technology)
Session VII: Circuits and Algorithms
Chair: Hiroshi Kawaguchi (Kobe University)
High Speed Pulse-based Flip-Flop with Pseudo MUX-type Scan for Standard Cell Library
Min-su Kim, SangShin Han, KyoungKuk Chae, Chung-Hee Kim, Gunok Jung, Kwangil Kim, JinYoung Park, Youngmin Shin, Sung-Bae Park, Young-Hyun Jun, Bai-Sun Kong (Sungkyunkwan University / Samsung Electronics)
Design of a Low-power High-performance 64-bit Carry Select Adder
Zhi-Hui Kong and Kiat-Seng Yeo (Nanyang Technological University)
A Low-energy GF(2^4m) Multiplier for Security in Wireless Sensor Networks
Kealan McCusker, Noel O’Connor, and Dermot Diamond (Dublin City University)
Fast Algorithms for Finding Minimum Leakage Vector
Zhang Mingming, Chang Xiaotao, and Zhang Zhimin (Institute of Computing Technology, Chinese Academy of Sciences)
Power Gating and Supply Control for Low Standby Leakage Power of
VLSI Circuits
Sewan Heo, Hyung-Ock Kim, and Youngsoo Shin (KAIST)
An FPGA-based Application-specific Protocol Engine for Interactive Visual Communication and Its Applications
Minoru Inamori, Takayuki Onishi, and Jiro Naganuma (NTT)
April 21, 2006
Session VIII
Chair: Masato Suzuki (Matsushita Electric Industrial Co., Ltd.)
Keynote Presentation 2
Computing with FPGAs
Oskar Mencer (Imperial College London)
Session IX
Chair: Jiro Naganuma (NTT)
Invited Presentation 2
COOL Applications for Petascale Computing
Eng Lim Goh (Silicon Graphics, Inc.)
Session X: Performance Evaluations
Chair: Udo Walterscheidt (Intel)
Performance Evaluation of Heterogeneous Chip Multi-Processor with MP3 Audio Encoder
Hiroaki Shikano, Yuki Suzuki, Yasutaka Wada, Jun Shirako, Keiji Kimura, and Hironori Kasahara (Waseda University / Hitachi)
Modeling and Analysis of the System Bus Latency on the SoC Platform
Je-Hoon Lee, Eun-Ju Choi, and Kyoung-Rok Cho (Chungbuk National University)
Evaluation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Array
Jackson Pang, Albert Liddicoat, Jesse Ralston, Paula Pingree, and J.Leigh Torgerson (Jet Propulsion Laboratory / California Polytechnic State University)
Session XI: Reconfigurable SoCs
Chair: Yoshio Hirose (Fujitsu Lab.)
Flexible Engine: A Dynamic Reconfigurable Accelerator with High Performance and Low Power Consumption
Tomoyuki Kodama, Takanobu Tsunoda, Masashi Takada, Hiroshi Tanaka, Yohei Akita, Makoto Sato, and Masaki Ito (Hitachi / Renesas Technology)
Adaptive Computing on the Dynamically Reconfigurable Processor
Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, and Hideharu Amano (Keio University / NEC)
Performance Evaluation of Reconfigurable Processing Array in Area Efficiency and Operating Frequency
T. Matsumoto, K. Kimura, H. Takano, T. Amatsubo, K. Mori, K. Senda, S. Inoue and M. Matsui (Toshiba)
An SoC with Reconfigurable Debug Infrastructure
Jacob Bower, Oskar Mencer, Wayne Luk, and Miron Abramovici (Imperial College London / DAFCA)
Session XII: Panel Discussions
Is reconfigurable LSI going major?
Chair: Hideharu Amano (Keio University)
Panelist: Oskar Mencer (Imperial College London)
Eng Lim Goh (Silicon Graphics, Inc.)
Tomoyoshi Sato (IP Flex)
Toru Awashima (NEC)
Haruyuki Tago (Toshiba)
Closing Remarks
Kunio Uchiyama, Program Committee Chair