Advance Program

IEEE COOL Chips 24 Final Program [pdf] is  here.

COOL24 Zoom Usage Guide [pdf] is here.

**All programs are in JST (UTC+9)

Wed. April 14, 2021
8:30-10:00Special Invited Lecture 1
Co-chairs: Takatsugu Ono (Kyushu Univ.), Chikafumi Takahashi (NSITEXE)
"Reducing Errors in Quantum Computation via Program Transformation",
Moinuddin Qureshi (Georgia Institute of Technology, USA)(Abstract, Bio)
10:00-10:30Break
10:30-12:00Special Invited Lecture 2
Co-chairs: Takatsugu Ono (Kyushu Univ.), Shotaro Shintani (NSITEXE)
"Processor Hardware Security",
Jakub Szefer (Yale University, USA)(Abstract, Bio)
12:00-13:00Lunch Break
13:00-14:30Special Session I: Panel Discussion
"Hot" Techs for "Cool" AI Computing: Do We have Enough Tricks?
Organizer and Moderator: Masato Motomura (Tokyo Tech, Japan)(Abstract, Bio)
14:30-15:00Break
15:00-15:50Special Session II: Keynote Presentation 1
Co-chairs: Fumio Arakawa (Univ. of Tokyo), Yasuo Unekawa (Toshiba Electronic Devices & Storage)
"Why Preferred Networks Made MN-Core?",
Yusuke Doi (Preferred Networks, Japan)(Abstract, Bio)
15:50-16:00Break
16:00-18:00Poster Session
Co-chairs: Koji Hashimoto (Fukuoka Univ.), Takumi Uezono (Hitachi)
Thu. April 15, 2021
9:00-9:10Session I: Welcome and Opening Remarks
Co-chairs: Yuki Kobayashi (NEC), Takuya Nakaike (IBM)
Kunio Uchiyama, Chair of the Organizing Committee
Tadao Nakamura (Chair of Steering Committee)
Jose Renau (Chair of IEEE/CS TCMM)
Hiroyuki Tsuda (President of IEICE ES)
9:10-10:00Session II: Keynote Presentation 2
Co-chairs: Yuki Kobayashi (NEC), Takuya Nakaike (IBM)
"虎穴に入らずんば虎子を得ず: Domain-specific Processors make for Cool Solutions",
Avi Baum (Hailo, Israel) (Abstract, Bio)
10:00-10:10Break
10:10-11:00Session III: Application Specific Systems with FPGAs
Co-chairs: Ryohei Kobayashi(Univ. of Tsukuba), Yasutaka Wada (Meisei Univ.)
10:10-10:35"Hybrid Network of Packet Switching and STDM in a Multi-FPGA System",
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano (Keio University, Japan)
10:35-11:00"High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory",
Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)
11:00-11:10Break
11:10-12:00Session IV: Keynote Presentation 3
Co-chairs: Teruaki Sakata (Hitachi), Masato Suzuki (Socionext)
"High-Efficiency Inferencing for Scalable Machine Learning",
Art Swift (Esperanto Technologies, USA)(Abstract, Bio)
12:00-13:00Lunch Time Break
13:00-13:50Session V: Deep Learning Acceleration I
Co-chairs: Hiroyuki Yuichiro Shibata (Nagasaki Univ.), Kazushi Kawamura (Tokyo Institute of Tech.)
13:00-13:25"An Energy-efficient Deep Neural Network Training Processor with Bit-slice-level Reconfigurability and Sparsity Exploitation",
Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, and Hoi Jun Yoo (KAIST, Korea)
13:25-13:50"In Search of the Performance- and Energy-Efficient CNN Accelerators",
Stanislav Sedukhin, Yoichi Tomioka, Kohei Yamamoto (The University of Aizu, Oki Electric Industry, Japan)
13:50-14:10Break
14:10-15:00Session VI: Keynote Presentation 4
Co-chairs: Yuetsu Kodama(Riken), Yasushi Inoguchi (JAIST)
"Codesign and System of the Supercomputer "Fugaku"",
Mitsuhisa Sato (Riken, Japan)(Abstract, Bio)
15:00-15:10Break
15:10-16:00Session VII: High Performance Processors
Co-chairs: Ryusuke Egawa (Tokyo Denki Univ.), Hiroyuki Takizawa (Tohoku Univ.)
15:10-15:35"Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip",
Eishi Arima, Yuetsu Kodama, Tetsuya Odajima, Miwako Tsuji, Mitsuhisa Sato (University of Tokyo, Riken, Japan)
15:35-16:00"A Timing Aware Connectivity Optimization Technique for Improving Energy Efficiency of High-Performance CPUs",
Ayan Datta, Karanvir Singh, Arpita Dutta, Kousik Debnath (Intel, India)
16:00-16:30Break
16:30-18:30Online Social Hour
Fri, April 16, 2021
9:00-9:40 Session VIII: Invited Presentation 1
Co-chairs: Yukinori Sato (Toyohashi Univ. of Technology), Kunio Uchiyama (AIST)
"Architectural Challenges in the Era of New Technologies and Extreme Heterogeneity",
Anastasiia Butko (Lawrence Berkeley National Laboratory) (Abstract, Bio)
9:40-10:00Break
10:00-10:50Session IX: Memory
Co-chairs: Kotaro Shimamura (Hitachi), Masanori Muroyama (Tohoku Institute of Tech.)
10:00-10:25"A Metadata Prefetching Mechanism for Hybrid Memory Architectures",
Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi (Tohoku University, Japan)
10:25-10:50"Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-standby and Instant-powerup Embedded Memory on IoT",
Takaki Urabe, Hiroyuki Ochi, and Kazutoshi Kobayashi (Kyoto Institute of Technology, Ritsumeikan University, Japan)
10-50-11:10Break
11:10-11:50Session X: Invited Presentation 2
Co-chairs: Akihiro Hashiguchi (Sony), Yoshio Hirose (Fujitsu)
"The CMOS image sensor Advance in key technology and the Introduction of Next-generation image sensor",
Akito Kuwabara (Sony Semiconductor Solutions, Japan) (Abstract, Bio)
11:50-13:20Lunch Time Break
13:20-14:10Session XI: Deep Learning Acceleration II
Co-chairs: Shunsuke Sasaki (Toshiba Electronic & Devices Storage), Ryuichi Sakamoto (Univ. of Tokyo)
13:20-13:45"LSFQ: A Low Precision Full Integer Quantization for High-Performance FPGA-based CNN Acceleration",
Zhenshan Bao, Kang Zhan, Wenbo Zhang, Junnan Guo (Beijing University of Technology, China)
13:45-14:10"Training Low-Latency Spiking Neural Network through Knowledge Distillation",
Sugahara Takuya , Renyuan Zhang , and Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)
14:10-14:20Poster Award and Closing Remark
Makoto Ikeda, Program Committee Co-chair (Univ. of Tokyo)