COOL Chips XVI
Yokohama Joho Bunka Center (Yokohama Media & Communications Center),
Yokohama, Japan
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Advance Program


Here, COOL Chips XVI Final Program [pdf] is uploaded.

(As of 10 April 2013)     

Wednesday, April 17, 2013    Main Hall (7th Floor)
13:00-15:30 Special Session 1
Chair: Hiroyuki Tomiyama (Ritsumeikan University)
 13:00-15:30 STHORM: A Multi-Processor Platform and Programming Environment
Pierre G. Paulin (STMicroelectronics, Canada)  (Abstract, Bio)
 15:30-16:00 Break
16:00-18:30 Special Session 2
Chair: Hiroyuki Tomiyama (Ritsumeikan University)
 16:00-18:30 Hot Research Issues in Main Memory Subsystem
Jung Ho Ahn (Seoul National University, Korea), Sungjoo Yoo (POSTECH, Korea)  (Abstract, Bio)

Thurseday, April 18, 2013   Main Hall (7th Floor)
9:30-9:50 Session I: Welcome and Opening Remarks
Chair: Kazumasa Suzuki (Renesas Electronics)
Hiroaki Kobayashi,     Chair of the Organizing Committee
Donald. A. Draper,     Chair of TCMCOMP
Kiyomichi Araki,        President of Electronics Society, IEICE
Fumiko Hayashi,        Mayor of Yokohama City
9:50-10:40 Session II: Keynote Presentation 1
Co-chairs: Masato Suzuki (Panasonic), Yukinori Sato (JAIST)
 9:50-10:40 What Can Supercomputers Learn from Phones?
Michael McCool (Intel, USA)  (Abstract, Bio)
10:40-11:30 Session II: Keynote Presentation 2
Co-chairs: Kazumasa Suzuki (Renesas Electronics), Hiroyuki Igura (NEC)
 10:40-11:30 Next Generation Vector Supercomputer for Providing Higher Sustained Performance
Shintaro Momose (NEC)  (Abstract, Bio)
 11:30-11:40 Break
11:40-12:10 Session III : Poster Short Speeches
Chair: Koji Hashimoto (Fukuoka University)
 12:10-13:10 Lunch Time Break
 13:10-13:30 Poster Open: 7th floor poster show room
13:30-14:20 Session IV: Keynote Presentation 3
Co-chairs: Akihiko Hashiguchi (Sony), Yasuo Unekawa (Toshiba)
 13:30-14:20 CoolChips at the core of a healthier world
Bert Gyselinckx (IMEC, Netherlands)  (Abstract, Bio)
 14:20-15:20 Break   (Poster Open: 7th floor poster show room)
15:20-16:00 Session V: Invited Presentation 1
Co-chairs: Hideharu Amano (Keio University), Fumio Arakawa (Renesas Electronics)
 15:20-16:00 Zero Overhead State-Retention Power-Gating and Gate-Bias on a Dual-Core ARM Cortex-A5MP Processor for 50-80% Idle Power Reduction
James Myers (ARM, UK)  (Abstract, Bio)
16:00-16:50 Session VI: Low Power Processors
Co-chairs: Abderazek Ben-Abdallah (University of Aizu), Kotaro Shimamura (Hitachi)
 16:00-16:25 Processor with 4.9-us Break-even Time in Power Gating Using Crystalline In-Ga-Zn-Oxide Transistor
Hidetomo Kobayashi, Kiyoshi Kato, Takuro Ohmaru, Seiichi Yoneda, Tatsuji Nishijima, Shuhei Maeda, Kazuaki Ohshima, Hikaru Tamura, Hiroyuki Tomatsu, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Jun Koyama, Shunpei Yamazaki (Semiconductor Energy Laboratory)
 16:25-16:50 RXv2 processor core for low-power microcontrollers
Sugako Otani, Hiroyuki Kondo, Naoshi Ishikawa (Renesas Electronics)
 16:50-17:00 Break
17:00-18:40 Session VII: Panel Discussions
  Topics: The Next Step in Processor Evolution
Organizer & Moderator: Yoshio Masubuchi (Toshiba)
Panelists:
     B. Gyselinckx (IMEC, Netherlands),   M. McCool (Intel, USA)
     S. Momose (NEC),   J. Myers (ARM, UK),   T. Yoshida (Fujitsu)
 18:40-19:00 Break
 19:00-21:00 Banquet

Friday, April 19, 2013   Main Hall (7th Floor)
9:30-10:20 Session VIII: Keynote Presentation 4
Co-chairs: Kohji Takano (IBM), Makoto Ikeda (University of Tokyo)
 9:30-10:20 Why and how “Watson” Answered Questions on the TV Quiz Show?
Hiroshi Kanayama (IBM Japan)  (Abstract, Bio)
10:20-11:00 Session VIII: Invited Presentation 2
Co-chairs: Yoshio Hirose (Fujitsu Laboratories), Ryusuke Egawa (Tohoku University)
 10:20-11:00 SPARC64TM X: Fujitsu's New Generation 16 Core Processor for UNIX servers
Toshio Yoshida (Fujitsu)  (Abstract, Bio)
 11:00-11:20 Break   (Poster Open: 7th floor poster show room)
11:20-12:35 Session IX: Many-Core Processors
Co-chairs: Byeong-Gyu Nam (Chungnam National University), Hajime Shimada (Nara Institute of Science and Technology)
 11:20-11:45 A Scalable 3D Heterogeneous Multi-Core Processor with Inductive-Coupling ThruChip Interface
Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura (Keio University)
 11:45-12:10 A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling
Junyoung Park, Injoon Hong, Gyeonghoon Kim, Youchang Kim, Kyuho Lee, Seongwook Park, Kyeongryeol Bong, Hoi-Jun Yoo (KAIST)
 12:10-12:35 Power Efficient Realtime Super Resolution by Virtual Pipeline Technique on a Server with Manycore Coprocessors
K. Ishizaka, T. Miyamoto, S. Akimoto, A. Iketani, T. Hosomi, J. Sakai (NEC)
 12:35-13:55 Lunch Time Break
13:55-14:35 Session X: Invited Presentation 3
Co-chairs: Yusuke Nitta (Renesas Electronics), Koyo Nitta (NTT)
  13:55-14:35 A 28nm HKMG Single-Chip Communications Processor with 1.5GHz Dual-Core Application Processor and LTE/HSPA+ Capable Baseband Processor
Takeshi Kataoka (Renesas Mobile)  (Abstract, Bio)
14:35-15:50 Session XI: HW/SW Technologies
Co-chairs: Hiroyuki Takizawa (Tohoku University), Yuetsu Kodama (University of Tsukuba)
 14:35-15:00 Automatic Parallelization, Performance Predictability and Power Control for Mobile-Applications
Dominic Hillenbrand, Akihiro Hayashi, Hideo Yamamoto, Keiji Kimura, Hironori Kasahara (Waseda University)
 15:00-15:25 HW/SW Approaches to Accelerate GRAPES in an FU Array
Wei Wang, Jun Yao, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, Weimin Zheng (Tsinghua University, China)
 15:25-15:50 Parallelization of Automotive Engine Control Software On Embedded Multi-core Processor Using OSCAR Compiler
Yohei Kanehagi, Dan Umeda, Akihiro Hayashi, Keiji Kimura, Hironori Kasahara (Waseda University)
 15:50-16:10 Break   (Poster Open: 7th floor poster show room)
16:10-17:00 Session XII: Resource Management
Chair: Jun Yao (Nara Institute of Science and Technology)
 16:10-16:35 Hardware Support for Resource Partitioning in Real-Time Embedded Systems
Tetsuro Honmura, Yuki Kondoh, Tetsuya Yamada, Masashi Takada, Takumi Nitoh, Tohru Nojiri, Keisuke Toyama, Yasuhiko Saitoh, Hirofumi Nishi, Mikiko Sato, Mitaro Namiki (Hitachi)
 16:35-17:00 A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms
Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi (Tohoku University)
17:00-17:50 Session XIII: 3D Technologies
Co-chairs: Yuichiro Shibata (Nagasaki University), Yasutaka Wada (NEC)
 17:00-17:25 Dynamic Power On/Off Method for 3D NoCs with Wireless Inductive-Coupling Links
Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano (Keio University)
 17:25-17:50 Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGA
Vinod Pangracious, Habib Mehrez, Zied Marakchi (University of Pierre and Marie Curie Paris, France)
17:50-18:10 Poster Award and Closing Remark
Makoto Ikeda, Program Committee Co-chair (University of Tokyo)